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[AK8452] ms0955-e-00 2008/03 1 device outline afe block the AK8452 is a +3.3 v, two channel 16 bit 10m sps adc which integrates on-chip offset adjust dac, gain adjust pga, cds circuit and <4.5~5.7v> 3 channel led drivers. led drive block this product is the 3 channel led driver who drives the led of the anode common in the constant current. the current to pass for each cha nnel can be adjusted by the external resistance and the register setting. also, it has the control pins which turn on or off the current. features afe block ? ccd i/f number of channels 2 channel range 1.98 vpp (typ.) signal input range 0~3.3v @ dc direc t coupled input mode at avdd = 3.3 v integrated on-chip cds circuit compatible with both positive an d negative signal polarities ? adc maximum conversion rate 10 msps (5msps/ch.) 8msps max. @1ch. mode resolution 16 bit (straight binary code) ? black level correction dac correctable range 240 mv (typ.) resolution 8 bit ? gain adjust adjustable range 0 db ~ +13.9 db (typ.) (1.0 ~ 4.9) resolution 6 bit ? total performance ( input ~ video adc ) output noise 6 lsb rms (typ.) @ pga gain = 0 db setting ? data output 2 bit wide or 4bit wide ? power supplies analog part: +3.3v 5 % / digital output part: +3.3v 0.3v ? cpu i/f 3-wire serial interface (write only) clock, data are commonly shared with a/d data output pins ? power dissipation 175 mw (typ.) with dc direct coup led input mode at avdd= 3.3v ? operating temperature range 0 c ~ +70 c ? package 28 pin qfn ? vref output for ccd: 1.1v 100mv. 10ma(max.) led drive block AK8452 2 channel-input 16 bit 10msps adc akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 2 operation voltage(lvdd) 4. 5v~5.7v absolute maximum voltage 6.5v operating temperature range 0 ~ 70 c led driver current red 60ma(adjustment external resister:20m~60ma) green: (programmable: red - 20% ; 4% step ) blue (programmable: red - 20% ; 4% step ) usable vf range of the led is from 1.5v to . the resistance for the current regulation is usable in 1/16w -type. the number of channels of applying an current to the led is at the same time to one or two. when the external resistance value becomes the assumption outside, it has the protection circuit which doesn't make the electric current which flows through the led equal to or more than 150ma30%. rch current accuracy 53 ~ 67ma(by 60ma setting) led current rise / fall time less than 10 s (10% ? 90%) led vf range 1.5v(min.) ~ (max.) application a light source driver for cis module of mfp akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 3 block diagram cisin0 vclp vcom vrp vrn tsmp mcl k cds s/h 8bit dac pga 16bit adc output control d0/sdcl k sdenb a vdd a vss reference voltage 16 6 d1/sdata control registers 8 drvdd drvss dc connect mode cds mode clamp switch v refo resetb d2 d3 current r sw sw current g current b tg sw led_b led_g led_r iref ledb_en ledg_en ledr_en lvdd lvss lvdd 5.5v(4.5-5.7v) cisin1 cds s/h pga 8bit dac 8 block diagram 6 akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 4 pin functions no. name io pd description 1 iref i led current setting external resister pin 2 vrefo o hi-z reference voltage output :1.1v external capacitor : 0.33 3 cisin0 i sensor signal input 4 vclp io (note 1) sensor reference level input at dc direct coupled mode clamp level output at cds mode (external cap.: 0.1 f) 5 cisin1 i sensor signal input 6 avss pwr analog ground 7 avdd pwr analog power supply 8 led_r o hi-z led output pin r 9 lvdd pwr led power supply 10 lvss pwr led ground 11 led_g o hi-z led output pin g 12 led_b o hi-z led output pin b 13 ledr_en i led control input r 14 ledg_en i led control input g 15 ledb_en i led control input b 16 d0/sdclk io (note2) sdenb=high ; a/d data output : lower bit (d0) sdenb=low ; serial interface clock input 17 d1/sdata io (note2) sdenb=high ; a/d data output : d1 bit sdenb=low ; serial interface data input 18 drvss pwr a/d output buffer ground 19 drvdd pwr a/d output buffer power supply 20 d2 o h or l (note3) a/d data output : d2 bit 21 d3 o h or l (note3) a/d data output : upper bit (d3) 22 sdenb i serial interface enable 23 mclk i main clock 24 tsmp i sampling timing 25 resetb i reset pin : active low, on chip pull-up resister : 100k (typ.) 26 vcom o hi-z internal reference voltage : external capacitor 0.1 f 27 vrn o l (note4) adc negative reference voltag e : external capacitor 0.1 f 28 vrp o l (note4) adc positive reference voltag e : external capacitor 0.1 f i: input , o: output , pwr: power/ground pin * connect the radiation pad in solder side of the package and analog ground (avss) for the exothermicity improvement. (note 1) it will be input on dc mode, be hi-z on ccd mode. (note 2) please be input state. (note 3) it will be h or l since pd mode. (note 4) it is connect with avss via internal resistance. akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 5 pin allocation 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 sdenb mcl k tsmp resetb vcom vrn vrp ledg_en ledr_en led_b led_g lvss lvdd led_r 15 16 17 18 19 20 21 d3 d2 drvdd drvss d1/sdata d0/sdclk ledb_en iref vrefo cisin0 vclp cisin1 avss avdd AK8452vn top view akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 6 circuit block description ? sensor interface part circuit to sample & hold input signal which is fed on cisin pin. signal input range is 1.98v (typ.). there are two input modes, dc direct coupled mode and cds mode. in dc direct coupled mode, positive polarity signal is handled. in cds mode , negative polarity signal is handled. signal reference voltage should be in put on vclp pin in dc direct coupled mode. in cds mode, voltage level to clamp signal is intern ally generated and it is output on vclp pin. ? black level correction circuit circuit to add an offset voltage to the samp led signal level. voltage range of dac which generates offset is 240 mv (typ.) and its resolution is 8 bit. ? pga part circuit to adjust signal amplitude, prior to ad conversion. adjustable gain range is from 0db to 13.9db ( typ. ) (1.0 ~ 4.9) an d its resolution is 6 bit. ? adc part ad conversion circuit to convert into digital data an analog signal after both black level correction and gain adjustment are made. its re solution is 16 bit with its maximum conversion rate of 10msps. data output is in a straight binary code. 0000h is output at black level input ( 0vpp input ) and ffffh is output at white level input ( maximum input ). ? output control part a 16 bit-wide 2ch adc output data is re-arranged into 2 bit 8 cycle2ch or 4bit 4cycle2ch stream at this part. in single edge mode operation, data is output at the rising edge of mclk. in double edge mode operation, it is output at both rising and falling edges of mclk. output mode is 2bit or 4bit by single mode, only 2bit on double mode. particulars is on p35 ~ p37. ? reference voltage generator circuit to generate internal reference volt ages. clamp reference voltage vclp, internal common voltage vcom and adc reference voltages vrp and vrn are generated. each reference voltage is output on respective device pins. for voltage stabilization, capacitors should be connected between respective pins and avss. ? led driver part this product generates has 3 channel led driver to drive rgb constant current. use the on/ off digital terminal to control the constant current. ? serial interface part a 3-wire interface circuit to access setting-regis ters. sdclk (clock) and sdata (data) pins are shared with d0 and d1 pins of adc data output . when sdenb pin is at low, d0 and d1pins function as sdclk and sdata input pins. in or der to avoid both sdclk and sdata pins to become floating condition, prop er pull-down resistors should be connected between d0 / sdclk pin, d1 / sdata pin and avss respectively. akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 7 absolute maximum ratings voltages are referenced to corresponding ground level. avss = drvss =lvss= 0v item symbol min. max. unit remarks power supplies analog power supply output buffer power supply ledd power supply avdd drvdd lvdd ? 0.3 ? 0.3 ? 0.3 4.6 4.6 6.5 v v v digital input voltage vtd ? 0.3 avdd+0.3 v analog input voltage vta ? 0.3 avdd+0.3 v storage temperature tstg ? 65 150 c operation under a condition exc eeding above limits may cause perm anent damage to the device. normal operation is not guaranteed under the above extreme conditions. recommended operating conditions voltages are referenced to corresponding ground level. avss = drvss=lvss = 0v item symbol min. typ. max. unit remarks power supplies analog power supply output buffer power supply ledd power supply avdd drvdd lvdd 3.135 3.0 4.5 3.3 3.3 5.5 3.465 3.6 5.7 v v operating temperature ta 0 70 c please power on avdd and lvdd the same time or avdd first. (when avdd becomes later, power on avdd within 100 ms after lvdd on. ) electrical characteristics ? dc characteristics (avdd=3.135~3.465v, drvdd=3.0~3.6v, ta=0 70 c, unless otherwise specified) item symbol pin min. typ. max. unit remarks h level input voltage vih note 1,2 note 4,5 0.7 avdd v l level input voltage vil note 1,2 note 4,5 0.3 avdd v h level output voltage voh note 3 0.7 drvdd v ioh= ? 2ma l level output voltage vol note 3 0.3 drvdd v iol=2ma input leakage current 1 il1 note 1,5 ? 10 10 a input leakage current 2 il2 note 2 ? 69.3 10 a apply 0v ~ avdd high-z leakage current ilz note 4 ? 10 10 a pull-up resistor rpu note 2 50 100 150 k (note 1) tsmp, mclk, sdenb (note 2) resetb (note 3) d0, d1 (at sdenb=high) , d2, d3 (note 4) sdata, sdclk (at sdenb=low ) (note 5) ledr_en, ledg_en, ledb_en akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 8 ? afe block, analog characteristics (avdd=3.3v, drvdd=3.3v, mclk=40mhz , 2ch. single edge mode, ta=25 c, unless otherwise specified) item min. typ. max. unit remarks reference voltage vcom voltage vrp voltage vrn voltage 1.4 1.9 0.9 1.5 2.0 1.0 1.6 2.1 1.1 v v v vref voltage at current sink error at current source error 1.0 - 0.1 1.1 1.2 +0.1 v v v band gap error @ i=10ma ( diff. @i=0ma) @ i= - 10ma( diff. @i=0ma) analog input maximum signal input level 1.98 v p-p ?0.7 0 0.7 db at dc mode (note 1) absolute gain ?1.50 ?0.60 0.30 db at cds mode (note 1) 1 5 msps @2ch mode (per 1ch) sampling rate 1 8 msps @1ch mode input reference level 0 1.1 1.5 v at dc mode vclp input resistence(cisin side) 10 60 k at dc mode(note 11) vclp input resistence(vclp side) 5 30 k at dc mode(note 11) input signal range 0 avdd v at dc mode note 2 clamp level (vclp voltage) 1.98 2.08 2.18 v at cds mode clamp resister 7 10 k at cds mode cds advantage -40 db (note 10) black level correction dac resolution 8 bit (note 3)test mode correctable range 215 240 265 mv at dc mode (note 4) internal offset voltage ?50 50 mv (note 5) pga(programmable gain amp.) circuit resolution 6 bit 0 db min. gain max. gain 13.3 13.9 14.5 db (note 6) video adc resolution 16 bit dnl ?16 +16 lsb inl ?128 32 +128 lsb crosstalk crosstalk 64 lsb (note 12) noise 6 lsb rms pga min. output noise 16 lsb rms pga max. power consumption 48 68 ma at dc mode (note 7) 55 77 ma at cds mode (note 7) analog part power dissipations 0.1 ma at power down (note 8) digital output driver power dissipation 5 10 ma (note 7)(note 9) (note 1) 0db is defined at the gain where adc output reaches its full-scale when 1.98vpp signal is input with pga setting at 00h. (note 2) cisin input signal must be in this range which is referenced to avss. akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 9 (note 3) monotonicity guaranteed. (note 4) 50 mv of the total correctable range is used for internal offset adjustment. (note 5) it defines that a boundary point of adc output codes between 0000h and 0001h exists within 50mv range of the offset adjustment dac setting when 1.1v is fed on cisin & vclp pins in dc direct coupled mode, and when pga gain is set to 0db. (note 6) relative value to the gain at pga setting is 00h. (note 7) a full-scale minus 2 db, 1 mhz sine-w ave signal is input. (@2ch mode, 4bit bus (note 8) a clock supply to mclk is stopped. (note 9) at the capacitive load is 20pf. (note 10) condition: input signal frequency : 1m hz, noise frequency : 0.1mhz, signal : noise = 10:1.no shipping inspection. (note 11) afe2ch. /single edge/4bit output mode (note 12) target channel pga gain at max, the other channel pga gain at minimum values. then measure how much the output code of the target channel to be measured fluctuates when input to the measured channe l is fixed and a full-scale minus 1 db step signal is input on all other channels. ? ledd block, analog characteristics (avdd=3.3v, lvdd=5.5, mclk=40m hz, single edge mode, ta=25 c, unless otherwise specified) item min. typ. max. unit remarks led drive current range 20 60 ma the led protection circuit activation current 105 150 195 ma led current (including resistance accuracy) (red) 53 60 67 ma ? there is possibility to adjust the typical value after es evaluation. it adjusts together with the min./max. value. iref resister =4.7k1% led pin voltage =2.0v(note 1) led current red green blue 95 95 100 105 105 % % % iref resister =4.7k1% led pin voltage =2.0v relative value led current accuracy (green,blue) 94.8 90.7 86.5 82.3 78.2 74.0 69.8 100 95.8 91.7 87.5 83.3 79.2 75.0 70.8 96.8 92.7 88.5 84.3 80.2 76.0 71.8 % % % % % % % % led pin voltage =0.5v 000 001 010 011 100 101 110 111 led current led pin voltage dependence -2.5 2.5 % led pin voltage =2.0v reference lvdd power consumption 0.6 1.5 ma except led drive current akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 10 (note 1) iref resister(k) = 60 [red led current(ma)] 4.7(k ) . and [red led current] can be set within the range of 20ma60ma . (avdd=3.135~3.465v, lvdd= 4.5~5.7 v, ta=0 70 c, unless otherwise specified) item min. typ. max. unit remarks led pin voltage 0.5 v led vf 1.5 4.8 v when lvdd<5.3v case, vf(max.)=lvdd-0.5v ledd block, switching characteristics (avdd=3.135~3.465v, lvdd= 4.5~5.7 v, ta=0 70 c, unless otherwise specified) no. item min. typ. max. unit condition 1 led current rise time 10 sec 2 led current fall time 10 sec 3 reset valid setup time ledb_en(0.7avdd):base position 0.1 sec ledb_en(0.7avdd) to ledr_en(0.3avdd) ledg_en(0.3avdd) 4 count up setup time ledb_en(0.3avdd):base position 0.1 sec ledb_en(0.3avdd) to ledr_en(0.7avdd) ledg_en(0.7avdd) 5 reset invalid setup time ledb_en(0.3avdd):base position 0.1 sec ledb_en(0.3avdd) to ledr_en(0.3avdd) ledg_en(0.3avdd) ledr_en ledg_en ledb_en 0.3avdd ledr,g,b current 90% 10% 0.7avdd 1 9t led*_en through mode akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 11 ledr_en ledg_en ledr,g,b current 0.3avdd 0.7avdd 0.3avdd 0.7avdd ledb_en (reset) 0.3avdd 90% 10% 0.7avdd 0.3avdd 1 2 3 4 5 except the through mode akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 12 afe block, switching characteristics (avdd=3.135~3.465v, drvdd=3.0~3.6v, ta=0 70 c , unless otherwise specified) no. item pin min. typ. max. unit condition 25 125 mode 1(note 2) 31.2 250 mode 2(note 2) 15.6 125 mode 3(note 2) 1 mclk cycle time (t) mclk 31.2 250 ns mode 4(note 2) 12.5 mode 1(note 2) 12.5 mode 2(note 2) 7.8 mode 3(note 2) 2 mclk h / l width mclk 15.6 ns mode 4(note 2) 3 tsmp setup time (referenced to mclk ) tsmp 5 ns note 1 4 tsmp hold time (referenced to mclk ) tsmp 5 ns note 1 5 aperture delay (referenced to mclk ) cisin 2 ns data level 6 aperture delay (referenced to mclk ) cisin 2 ns reference level 8t mode 1(note 2) 4t mode 2(note 2) 8t mode 3(note 2) 7 tsmp cycle (mclk period-unit ) tsmp 4t mode 4(note 2) 8 data output delay (referenced to mclk or mclk ) d0, d1,d2,d3 2 2 25 20 ns ns at load: 20pf drivability : normal mode : x2 mode 6 1ch 4bit bus r 5 1ch 2bit bus r 9 pipeline delay (smp period-unit ) d0, d1,d2,d3 3 2chmode r 10 reset pulse width resetb 50 ns note 1) number of mclk rising edges during tsmp = h duration is allowed to be 1 to 3 times in 1ch,single edge, 2bit bus mode operation, and only a single edge is allowed in the other mode operation. note 2) mode 1 ~ mode 4 explanation mode 1 : afe 2ch./ single edge/ 4bit bus mode mode 2 : afe 1ch./ single edge/ 4bit bus mode mode 3 : afe 1ch./ single edge/ 2bit bus mode mode 4 : afe 1ch/ double edge/ 2bit bus mode akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 13 cisin1 sample point mcl k tsmp 0.7avdd 0.7avdd 1 (t) 4 3 shd (internal) 5 0.5avdd 2 2 0.7avdd 0.3avdd 0.3avdd 43 7 cisin0 sample point sampling timing (dc mode, afe 2ch, single edge, 4 bit bus mode ) mcl k tsmp 0.5avdd 1 2 shd (internal) 5 shr (internal) 6 2 0.3avdd 0.7avdd 0.7avdd 4 3 0.3avdd 43 7 cisin1 sample point sample point cisin0 sample point sample point sampling timing (cds mode, afe 2ch, single edge, 4 bit bus mode ) akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 14 shd (internal) cisin0 5 sample point mcl k tsmp 0.7avdd 0.7avdd 1 (t) 4 3 0.5avdd 2 2 0.7avdd 0.3avdd 0.3avdd 43 7 sampling timing (dc mode, afe 1ch, single edge, 4 bit bus mode ) shd (internal) cisin0 5 sample point shr (internal) 6 sample point mcl k tsmp 0.7avdd 0.7avdd 1 (t) 4 3 0.5avdd 2 2 0.7avdd 0.3avdd 0.3avdd 43 7 sampling timing (cds mode, afe 1ch, single edge, 4 bit bus mode ) akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 15 mcl k tsmp 0.7avdd 0.7avdd 1 (t) 4 3 shd (internal) cisin0 5 sample point 0.5avdd 2 2 0.7avdd 0.3avdd 0.3avdd 43 7 sampling timing (dc mode, afe 1ch, single edge, 2 bit bus mode ) mcl k tsmp 0.5avdd 1 2 shd (internal) cisin0 5 sample point shr (internal) 6 sample point 2 0.3avdd 0.7avdd 0.7avdd 4 3 0.3avdd 43 7 sampling timing (cds mode, afe 1ch, single edge, 2 bit bus mode ) akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 16 shd (internal) cisin0 5 sample point mcl k tsmp 0.7avdd 0.7avdd 1 (t) 4 3 0.5avdd 2 2 0.7avdd 0.3avdd 0.3avdd 43 7 sampling timing (dc mode, afe 1ch, double edge, 2 bit bus mode ) shd (internal) cisin0 5 sample point shr (internal) 6 sample point mcl k tsmp 0.7avdd 0.7avdd 1 (t) 4 3 0.5avdd 2 2 0.7avdd 0.3avdd 0.3avdd 43 7 sampling timing (cds mode, afe 1ch, double edge, 2 bit bus mode ) akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 17 mclk d0, d1 0.7avd d 0.7drvdd 8 0.3avd d 0.3 drvd d d2, d3 data output timing ( single edge mode ) mclk d0, d1 0.7avd d 0.7d rvd d 8 0.3avd d 0.3 d rvd d 8 d2, d3 data output timing ( double edge mode ) resetb 10 0.3avdd 0.3avdd reset pulse width akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 18 n+1 n-3 n+2 n n+3 n-2 n-1 n+4 n cisin0,1 mclk tsm p shd (internal) d0 d3 pipeline delay (afe 2ch, sing le edge, 4 bit bus mode ) n+2 n-3 n-2 n+1 n+3 n+4 n+5 n n-5 n-4 n-6 n-7 n+ 6 n+ 7 n-1 n cisin0 mclk tsm p shd (internal) d0 d3 pipeline delay (afe 1ch, sing le edge, 4 bit bus mode ) n+2 n-2 n-1 n+1 n+3 n+4 n+5 n n-4 n-3 n-5 n-7 n+ 6 n+ 7 n+1 n cisin0 mclk tsmp shd (internal) d0 d1 pipeline delay (afe1ch, sing le edge, 2 bit bus mode ) n+2 n-2 n-1 n+1 n+3 n+4 n+5 n n-4 n-3 n-5 n-7 n+ 6 n+ 7 n+1 n cisin0 mclk tsmp shd (internal) d0 d1 pipeline delay (afe1ch, doub le edge, 2 bit bus mode ) akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 19 ? serial interface: switching characteristics ( avdd=3.135~3.465v, drvdd=3.0~3.6v ,ta= 0~70 c , unless otherwise specified) no. item pin min. typ. max. unit condition 1 clock period sdclk 0.1 10 mhz 2 clock pulse width (h duration) sdclk 40 ns 3 clock pulse width ( l duration ) sdclk 40 ns 4 sdenb setup time (to sdclk rising edge ) sdenb 80 ns 5 sdenb hold time (from sdclk rising edge ) sdenb 80 ns 6 data high-z delay (from sdenb falling edge ) d0, d1 0 40 ns 7 data enable delay (from sdenb rising edge ) d0, d1 0 40 ns 8 sdata setup time (to sdclk rising edge ) sdata 40 ns 9 sdata hold time ( from sdclk rising edge ) sdata sdenb 40 ns 10 sdclk,sdenb rise time sdclk sdenb 6 ns 11 sdclk,sdenb fall time sdclk sdenb 6 ns 12 sdenb high level pulse width sdenb 40 ns sdcl k sdata sdenb 0.7avdd 0.7avdd 8 0.3avdd 0.3avdd 9 0.3avdd 32 1 12 10 11 0.7avdd 10 11 0.7avdd 0.3avdd d0 4 d1 7 7 6 6 0.7dvdd 0.3dvdd 0.7dvdd 0.3dvdd 5 serial interface timing clock input pin sdclk and data input pin sdat a for serial interface are shared with a/d data output pins, d0 and d1 respectively. when sdenb becomes low, d0 and d1 are put into high-z conditions and it is enabled to inpu t sdclk and sdata. sdata is captured at the rising edge of sdclk. sdata is 16 bit lo ng. write ?zeros? first bit and from the 5 th bit to the 5 th bit. 2 nd ~4 th bits are assigned for register address where the 2 nd bit is msb and the 4 th bit is akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 20 lsb. 9 th ~ 16 th bits are assigned for data where the 9 th bit is msb and the 16 th bit is lsb. 16 and more rising edges of sdclk are required while sdenb is low, from the time to fall to the time to rise. when it is less than 16 ri ses, registers will not be written properly. if it is more than 16 rises while sdenb is low, from falling to rising, the last 16 edges become effective. there is a possibility that an erroneou s data will be written into registers if noises occur on d0 output / sdclk input pin and d1 output / sdata input pin when these pins are at high-z conditions. to avoid this, resistors shou ld be connected between d0 / sdclk pin, d1 / sdata pin and avss respectively to pull-down these pins. 0 0 sdenb d0 sdcl k d1 sdata a1a0 0 b7b6b5b4b3b2b1b0 0 high-z high-z 00 0 a2 register write akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 21 - power on reset a vdd resetb AK8452 100k 0.33 f a vdd resetb 3.135v a vdd rise time max. 10ms it becomes possible for the register writing after 100 ms. max. 100ms power on reset at the power-on, power-on-reset must be executed by using resetb pin. when a 0.33 uf external capacitor on resetb pin is used, the rise time of avdd must be shorter than 10 ms in order to assure proper power-on-reset operat ion. maximum time from avdd power-on to the release from power-on-reset is 100 ms. registers sh ould be written after waiting for longer than 100 ms after avdd power-on. as electric charge is retained in the external capacitor even after avdd is made to 0v, voltage on resetb pin does not go to 0v immediately. if avdd is powered-up again before resetb pin returns to 0v, a proper power-on-reset operation is not made. in order to assure proper power-on-reset operation when to power-up avdd again, it is required that avdd time to be kept at 0v is longer than 300 ms. if the 300 ms avdd time to be kept at 0v, is not obtainable, the device must be reset by applying a low pulse externally on resetb pin. akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 22 -register map sub adrs bits default value register name function 0h 7 6 5 4 3:2 1 0 0******* *0****** **0***** ***0**** ****00** ******0* *******0 rst md_ch out_dr md_ccd tmg_shr md_dblegg npd register reset ch. number, 1ch mode / 2ch mode output buffer driverbility input mode, cds mode / dc mode reference level sampling timing clock mode select power down mode 1h 7:0 10000000 dac0 offset dac0 setting 2h 5:0 **000000 pga0 pga0 gain setting 3h 7:6 5:3 2 1 0 00****** **000*** *****0** ******0* *******0 ledspeed shdset out_bs oen test_o timing setting output bus select output buffer enable output order select 4h 7:0 10000000 dac1 offset dac1 setting 5h 5:0 **000000 pga1 pga1 gain setting 6h 6 5:3 2:0 *0****** **000*** *****000 half g_current b_current led current half mode g current setting b current setting 7h 7:6 3:2 1:0 00****** ****00** ******00 a_cont tgmode tgcsel lower address access control tgmode register tgcsel register 8h 7:0 00000000 test test register 9h 7:0 00000000 test test register ah 7:0 10000000 test test register * address 08 ah is test register. access inhibit. akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 23 operation mode setting register 1 (address ?0000?, reset ?0000 0000? rst b7 register reset 0 1 register reset (at reset) release from reset when this bit is set to ?0?, all other registers are set to initial values, except for this bit. when this bit is ?0?, write operation into all ot her registers except for this bit is ignored. md_ch b6 channel number select 0 1 1ch mode (cisin0 active) 2ch mode note: when use the 1ch mode, please set the unused channel to gnd. out_dr b5 output buffer drivability 0 1 normal ( at reset ) 2 ( double ) when output buffer drivability is set to ?2?, maximum output current of the output buffers increases. this selection is used when the data output delay which is referenced to data capture clock becomes too large, due to capacitive loading. md_ccd b4 input mode 0 1 dc direct-coupled mode cds mode signal polarity which can be processed by the ak 8452 is determined by the type of input modes. in dc direct-coupled mode, it hand les positive polarity (signal is output toward higher voltage than reference level: vclp ) and in cds mode, it handles negative polarity (signal is output toward lower voltage than reference level). akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 24 tmg_shr:b[3:2] feed-through leve l sampling pulse (shr) position 00 01 10 11 2 mclk(1 ) delay from the data level sampling position 3 mclk(1.5 ) delay from the data level sampling position 4 mclk(2 ) delay from the data level sampling position 5 mclk(2.5 ) delay from the data level sampling position note ) in the brackets (value), it is the value when the operation frequency= 4 mclk. mclk tsmp shd (internal) shr (internal) r0b3~b2= 00b 01b 10b 11b data level sampling reference level sampling cisin afe 2ch/ single edge/ 4 bit bus mode input output timing mclk tsmp shd (internal) shr (internal) r0b3~b2= 00b 01b 10b 11b data level sampling reference level sampling cisin afe 1ch/ single edge/ 4 bit bus mode input output timing akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 25 mclk tsmp shd (internal) shr (internal) r0b3~b2= 00b 01b 10b 11b data level sampling reference level sampling cisin afe 1ch/ single edge/ 2 bit bus mode input output timing mclk tsmp shd (internal) shr (internal) r0b3~b2= 00b 01b 10b 11b data level sampling reference level sampling cisin afe 1ch/ double edge/ 2 bit bu s mode input output timing akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 26 md_dblegg b1 clock mode select 0 1 single edge mode double edge mode npd b0 power down setting 0 1 power down normal in the power down, regardless of the condition of sdenb, the logic of the following pin is as follows. d0/sdclk input d1/sdata input d2 h or l; fixed level (high or low depends on the previous condition.) d3 h or l; fixed level (high or low depends on the previous condition.) the table of each setting channel number clock mode outp ut bus sel. compatible / not 4 bit bus single edge 2 bit bus 4 bit bus 2ch double edge 2 bit bus 4 bit bus single edge 2 bit bus 4 bit bus 1ch double edge 2 bit bus akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 27 offset 0 data setting (address ?0001?, reset ?1000 0000? register dac output 00000000 00000001 00000010 -240.0mv -238.1mv -236.2mv ? ? ? ? 01111110 01111111 10000000 10000001 10000010 -3.8mv -1.9 mv 0 mv +1.9mv +3.8mv ? ? ? ? 11111101 +234.4mv 11111110 +236.3mv 11111111 +238.1mv mv] [ 256 / 480 240 x offset(x) + ? = ; x is setting value @ reset x= 128, offset(128)=0mv s/h black cal. ffh 00h 80h offset dac setting s/h output level cis signal after black cal. level pga adc max. min. output code the change of the level by the offset setting (dc direct mode = pos. polarity ) cds black cal. 00h ffh 80h offset dac setting cds output level cis signal(ccd type) after black cal. level pga adc min. max. output code the change of the level by the offset setting (cds mode = neg. polarity ) akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 28 pga0 gain setting ( address ?0010?, reset ?xx00 0000? register gain [ times ] 000000 1.003 000001 1.015 000010 1.029 000011 1.042 : : : : 111100 4.168 111101 4.400 111110 4.659 111111 4.950 ] [ ) 63 ( 16 80 0 . 2 98 . 1 times x gain(x) ? + = ; x is setting value @ reset x =0, gain(0)=1.0 times 0 1 2 3 4 5 0 16324864 setting value [dec] gain[times] 0 0.1 0.2 0.3 0.4 0.5 gain step [times] gain[times] step[times] gain curve (theoretical figure) ** the definition with the above pga gain is the value of pga simple substance. in dc direct mode, ( the positive-polarity ) is gained < pga gain's being duple > after offset adjustment in the voltage of the difference between the reference voltage which is inputted to the vclp terminal and the signal level ( the part of shd ). in cds mode , ( the negative electrode ), the voltage of the difference between the reference level ( the part of shr ) and the signal level ( the part of shd ) is gained absolute gain duple(-0.6db typ.) and it is < pga gain's being duple > after offset adjustment. akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 29 operation setting 2 ( address ?0011?, reset ?0000 0000?) ledspeedb[7:6] tsmp frequency select for adjust led timing led timing frequency diving ratio = 1 (1mhz <=tsmp frequency < 2.2mhz) led timing frequency diving ratio = 1/2 (2mhz <=tsmp frequency < 4.4mhz) led timing frequency diving ratio = 1/4 (tsmp frequency >=4mhz) inhibition led current tsmp mclk led*_en internal en signal ** by setting led _en off to on timing single edge mode/ bit output led current tsmp mclk led*_en internal en signal ** by setting led _en on to off single edge mode/ bit output akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 30 led current led*_en internal en signal tsmp mclk ** by 01 setting led _en off to on single edge mode/ bit output led current led*_en internal en signal tsmp mclk ** by setting led _en on to off single edge mode/ bit output tsmp mclk led current led*_en internal en signal ** by setting led _en off to on single edge mode/ bit output akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 31 tsmp mclk led current led*_en internal en signal ** by setting led _en on to off single edge mode/ bit output shdset b[5:3] shd timing 000 001 010 011 1xx it is delayed for 7(3.5) clocks than a data sampling position. it is delayed for 6(3) clocks than a data sampling position. it is delayed for 5(2.5) clocks than a data sampling position. it is delayed for 4(2) clocks than a data sampling position. shd ( input clock) = tsmp mclk tsmp shd (internal) 011b data level sampling cisin 010b 001b 000b 1xxb prohibited prohibited afe2ch / single edge / 4bit bus mode io timing akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 32 mclk tsmp shd (internal) 011b cisin 010b 1xxb 000b 001b afe1ch / single edge mode / 4 bit bus mode io timing mclk tsmp shd (internal) 011b data level sampling cisin 010b 001b 000b 1xxb afe1ch / single edge / 2 bit bus mode io timing mclk tsmp shd (internal) 011b cisin 010b 1xxb 000b 001b afe1ch / double edge / 2 bit bus mode io timing akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 33 out_bs b2 output bus size mode 0 1 2 bit bus mode 4 bit bus mode the table of each setting channel number clock mode output bus sel. compatible / not 4 bit bus single edge 2 bit bus 4 bit bus 2ch double edge 2 bit bus 4 bit bus single edge 2 bit bus 4 bit bus 1ch double edge 2 bit bus akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 34 cisin0 mclk tsmp b13 b12 b9 b5 b1 b13 b9 b5 b1 b8 b4 b0 b12 b8 b4 b0 b13 b9 b5 b1 b13 b9 b5 b1 b12 b8 b4 b0 b12 b8 b4 b0 b9 b5 b1 b8 b4 b0 b13 b12 b9 b8 d1 d0 b15 b14 b11 b7 b3 b15 b11 b7 b3 b10 b6 b2 b14 b10 b6 b2 b15 b11 b7 b3 b15 b11 b7 b3 b14 b10 b6 b2 b14 b10 b6 b20 b11 b7 b3 b10 b6 b2 b15 b14 b11 b10 d3 d2 cisin1 cisin0 cisin1 afe2ch / single edge / 4 bit bus mode io timing cisin0 mclk tsmp d1 d0 d3 d2 cisin1 b15 b11 b7 b3 b14 b10 b6 b2 b13 b9 b5 b1 b12 b8 b4 b0 b15 b11 b7 b3 b14 b10 b6 b2 b13 b9 b5 b1 b12 b8 b4 b0 b15 b14 b13 b12 b7 b6 b5 b4 b3 b2 b1 b0 afe1ch / single edge / 4 bit bus mode io timing akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 35 cisin0 mclk tsmp b15 b14 b13 b11 b9 b7 b5 b3 b1 b12 b10 b8 b6 b4 b2 b0 b15 b13 b11 b9 b7 b5 b3 b1 b14 b12 b10 b8 b6 b4 b2 b0 b5 b3 b1 b4 b2 b0 b15 b14 b13 b12 d1 d0 d3 d2 cisin1 afe1ch / single edge / 2 bit bus mode io timing cisin0 mclk tsmp d1 d0 d3 d2 cisin1 b15 b14 b13 b11 b9 b7 b5 b3 b1 b12 b10 b8 b6 b4 b2 b0 b15 b13 b11 b9 b7 b5 b3 b1 b14 b12 b10 b8 b6 b4 b2 b0 b3 b1 b5 b4 b2 b0 b15 b14 b13 b12 afe1ch / double edge / 2 bit bus mode io timing oen b1 output buffer enable 0 1 enable hi-z akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 36 test_o b0 output order select 0 1 pattern 0 pattern 1 afe2ch / single edge / 4 bit bus mode format mcl k tsmp b15 b14 b11 b10 b7 b6 b3 b2 b15 b14 b11 b10 b7 b6 b3 b2 d3 d2 b13 b12 b9 b8 b5 b4 b1 b0 b13 b12 b9 b8 b5 b4 b1 b0 d1 d0 patter n b15 b7 b14 b6 b13 b5 b12 b4 b11 b3 b10 b2 b9 b1 b8 b0 d3 d2 b15 b7 b14 b6 b13 b5 b12 b4 b11 b3 b10 b2 b9 b1 b8 b0 d1 d0 patter n 1(for tes t ) ch.0 ch.1 ch.0 ch.1 akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 37 afe1ch / single edge / 4 bit bus mode format mclk tsmp b15 b14 b11 b10 b7 b6 b3 b2 d1(d3) d0(d2) b13 b12 b9 b8 b5 b4 b1 b0 d1(d3) d0(d2) p attern 0 p attern 1 prohibited afe1ch / double edge / 2 bit bus mode mcl k tsmp b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 d1 d0 b15 b7 b14 b6 b13 b5 b12 b4 b11 b3 b10 b2 b9 b1 b8 b0 d1 d0 pat t er n patter n akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 38 afe1ch / single edge / 2 bit bus mode format mcl k tsmp b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 d1 d0 b15 b7 b14 b6 b13 b5 b12 b4 b11 b3 b10 b2 b9 b1 b8 b0 d1 d0 patter n patter n akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 39 offset dac1 data setting ( address ?0100?, reset ?1000 0000?) this value is ch1 offset dac setting the setting method is the same as the offset dac0 data setting register. pga1 gain setting ( address ?0101?, reset ?xx00 0000? this value is ch1 pga gain setting the setting method is the same as the pga0 gain setting register. akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 40 led setting 1 ( address ?0110?, reset ?x0000000? ) half:b6 led current half mode 0 1 normal mode the led output current value becomes 1/2. g_current b[5:3] green current setting [%] this value is a ratio with the red led. 000 100 001 95.8 010 91.7 011 87.5 100 83.3 101 79.2 110 75 111 70.8 b_current b[2:0] blue current setting [%] this value is a ratio with the red led. 000 100 001 95.8 010 91.7 011 87.5 100 83.3 101 79.2 110 75 111 70.8 akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 41 led setting 2 ( address ?0111?, reset ?00xx 0000? a_cont b[7:6] lower address (00h ~ 06h) accsess control 00 access enable ( normal operation 01 access disable 10 access disable 11 access disable it becomes impossible in writing a thing except "00" in b:[7:6] to write notes in lower-address (00h-06h). write "00" in b:[7:6] and use to be general. akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 42 tgmode b[3:2] operation 00 led*_en through mode 01 ledr_en r ? off ? g ? off ? b ? off : led switch order ledg_en g ? off ? b ? off ? r ? off : led switch order ledb_en led counter reset 10 ledr_en g ? off ? b ? off ? r ? off : led switch order ledg_en b ? off ? r ? off ? g ? off : led switch order ledb_en led counter reset 11 ledr_en b ? off ? r ? off ? g ? off : led switch order ledg_en r ? off ? g ? off ? b ? off : led switch order ledb_en led counter reset at led*_en through mode function ledr en ledg en ledb_en ledr ledg ledb ron ron gon bon bon at tg mode function ( following figure is example of tgmode =01 setting ) ledr en ledg en ledb_en ledr ledg ledb ron ron gon bon ron ron gon bon gon gon reset **when led*_en is set to on -> off -> on, please set the off width for at least 50 tsmp. **when led*_en is set on off -> on -> off, please set the on width for at least 50 tsmp. akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 43 tgcsel b[1:0] operation 00 when tgmode ?00? ; the led repeats on/off of 3 color in turn. 01 when tgmode ?00? ; the led repeats on/off, that the first only 2 color is alternate. 10 when tgmode ?00? ; only the first color led repeats on/off. 11 prohibited tgmode =01 setting example tgcsel= 00 ledr en ledg en ledb_en ledr ledg ledb ron ron gon bon ron bon gon bon gon gon tgcsel = 01 ledr en ledg en ledb_en ledr ledg ledb ron ron gon gon gon bon gon bon gon ron tgcsel = 10 ledr en ledg en ledb_en ledr ledg ledb ron ron ron gon gon gon gon gon ron ron akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 44 external circuit example dc direct mode cds mode * the radiation pad on the package solder side connect with analog ground (avss). 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 sdenb mclk tsmp resetb vcom vrn vrp ledg_en ledr_en led_b led_g lvss lvdd led_r 15 16 17 18 19 20 21 d3 d2 drvdd drvss d1/sdata d0/sdclk ledb_en iref vrefo cisin0 vclp cisin1 avss avdd AK8452vn top view drvdd:3.3v 0.1 f 4.7k 0.1 f 0.1 f 0.1 f 0.1 f 0.33 f min.10 k lvdd: 5.5v avdd:3.3v 0.33 f 0.1 f min.10 k reference voltage 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 sdenb mclk tsmp resetb vcom vrn vrp ledg_en ledr_en led_b led_g lvss lvdd led_r 15 16 17 18 19 20 21 d3 d2 drvdd drvss d1/sdata d0/sdclk ledb_en iref vrefo cisin0 vclp cisin1 avss avdd AK8452vn top view drvdd:3.3v 0.1 f 4.7k 0.1 f 0.1 f 0.1 f 0.1 f 0.33 f lvdd: 5.5v avdd:3.3v 0.33 f 0.1 f 0.1 f 0.1 f min.10 k min.10 k akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 45 package ? package dimension unit [mm] ? marking 1. marketing code :8452 2. date code :xxx week code :y the company management code 8 4 5 2 x xx y marking 4.00.1 4.00.1 b a 0.20.05 15 22 28 1 7 8 14 21 c0.2 0.2 2.0 0.05 0.40.05 m 0.05 s a b 2.6 2.6 2.0 s s 0.4 0.778 +0.022 -0.023 akm confidential
asahi kasei [AK8452] ms0955-e-00 2008/03 46 important notice z these products and their specifications are subject to change without notice. when you consider any use or application of th ese products, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, curre ncy exchange, or strategic materials. z akemd products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for th e use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuc lear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or dist ributor of akemd products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, an d the buyer or distributor agrees to assume any and all responsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. akm confidential

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